--

-- ****************************************************************************
--                                                                           --
--     Copyright @ 1999                                                      --
--                                                                           --
--     Tetraedre SARL,  chenes 19,   2072 Saint-Blaise,  Switzerland         --
--                                                                           --
-- ****************************************************************************
--                                                                           --
-- Filename  : tcdg.vhd                                                      --
--                                                                           --
-- ****************************************************************************
--                                                                           --
-- WARNING: This file is the property of Tetraedre SARL, Switzerland. This   --
-- file is protected by a copyright. The reading, copying, compilation,      --
-- synthesis and other use of this file is forbidden without a written       --
-- agreement signed by Tetraedre SARL, Switzerland.                          --
--                                                                           --
-- IN NO EVENT SHALL TETRAEDRE SARL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER--
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING   --
-- FROM, OUT OF OR IN CONNECTION WITH THIS DESCRIPTION OR THE USE OF IT.     --
--                                                                           --
-- ****************************************************************************





----------------------------------------------------------------------------
------------------------------------------------------------------ SUBKEY --
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subkey is
    port (
        key    : in  std_logic_vector(63 downto 0);
        sel    : in  std_logic_vector(3 downto 0);
        subkey : out std_logic_vector(47 downto 0)
    );
end;


---------- Architecture subkey ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subkey is
    signal kkey_1  : std_logic_vector(47 downto 0);
    signal kkey_2  : std_logic_vector(47 downto 0);
    signal kkey_3  : std_logic_vector(47 downto 0);
    signal kkey_4  : std_logic_vector(47 downto 0);
    signal kkey_5  : std_logic_vector(47 downto 0);
    signal kkey_6  : std_logic_vector(47 downto 0);
    signal kkey_7  : std_logic_vector(47 downto 0);
    signal kkey_8  : std_logic_vector(47 downto 0);
    signal kkey_9  : std_logic_vector(47 downto 0);
    signal kkey_10 : std_logic_vector(47 downto 0);
    signal kkey_11 : std_logic_vector(47 downto 0);
    signal kkey_12 : std_logic_vector(47 downto 0);
    signal kkey_13 : std_logic_vector(47 downto 0);
    signal kkey_14 : std_logic_vector(47 downto 0);
    signal kkey_15 : std_logic_vector(47 downto 0);
    signal kkey_16 : std_logic_vector(47 downto 0);
    signal q       : std_logic_vector(63 downto 0);
    signal s0_0    : std_logic_vector(47 downto 0);
    signal s0_1    : std_logic_vector(47 downto 0);
    signal s0_2    : std_logic_vector(47 downto 0);
    signal s0_3    : std_logic_vector(47 downto 0);
    signal s0_4    : std_logic_vector(47 downto 0);
    signal s0_5    : std_logic_vector(47 downto 0);
    signal s0_6    : std_logic_vector(47 downto 0);
    signal s0_7    : std_logic_vector(47 downto 0);
    signal s1_0    : std_logic_vector(47 downto 0);
    signal s1_1    : std_logic_vector(47 downto 0);
    signal s1_2    : std_logic_vector(47 downto 0);
    signal s1_3    : std_logic_vector(47 downto 0);
    signal s2_0    : std_logic_vector(47 downto 0);
    signal s2_1    : std_logic_vector(47 downto 0);

begin

    q <= key;


    P1 : process(q)
    begin
        kkey_1<=q(54)&q(13)&q(30)&q(4)&q(15)&q(47)&q(31)&q(7)&q(62)&q(55)&q(45)&q(22)&q(61)&q(29)&q(38)&q(39)&q(20)&q(6)&q(5)&q(63)&q(28)&q(37)&q(46)&q(23)&q(42)&q(36)&q(25)&q(10)&q(27)&q(60)&q(17)&q(34)&q(59)&q(11)&q(41)&q(35)&q(3)&q(43)&q(26)&q(1)&q(49)&q(44)&q(19)&q(50)&q(51)&q(2)&q(9)&q(33);
        kkey_2<=q(62)&q(21)&q(38)&q(12)&q(23)&q(55)&q(39)&q(15)&q(5)&q(63)&q(53)&q(30)&q(4)&q(37)&q(46)&q(47)&q(28)&q(14)&q(13)&q(6)&q(7)&q(45)&q(54)&q(31)&q(50)&q(44)&q(33)&q(18)&q(35)&q(1)&q(25)&q(42)&q(36)&q(19)&q(49)&q(43)&q(11)&q(51)&q(34)&q(9)&q(57)&q(52)&q(27)&q(58)&q(59)&q(10)&q(17)&q(41);
        kkey_3<=q(13)&q(37)&q(54)&q(28)&q(39)&q(6)&q(55)&q(31)&q(21)&q(14)&q(4)&q(46)&q(20)&q(53)&q(62)&q(63)&q(15)&q(30)&q(29)&q(22)&q(23)&q(61)&q(5)&q(47)&q(3)&q(60)&q(49)&q(34)&q(51)&q(17)&q(41)&q(58)&q(52)&q(35)&q(2)&q(59)&q(27)&q(36)&q(50)&q(25)&q(10)&q(1)&q(43)&q(11)&q(44)&q(26)&q(33)&q(57);
        kkey_4<=q(29)&q(53)&q(5)&q(15)&q(55)&q(22)&q(6)&q(47)&q(37)&q(30)&q(20)&q(62)&q(7)&q(4)&q(13)&q(14)&q(31)&q(46)&q(45)&q(38)&q(39)&q(12)&q(21)&q(63)&q(19)&q(9)&q(2)&q(50)&q(36)&q(33)&q(57)&q(11)&q(1)&q(51)&q(18)&q(44)&q(43)&q(52)&q(3)&q(41)&q(26)&q(17)&q(59)&q(27)&q(60)&q(42)&q(49)&q(10);
        kkey_5<=q(45)&q(4)&q(21)&q(31)&q(6)&q(38)&q(22)&q(63)&q(53)&q(46)&q(7)&q(13)&q(23)&q(20)&q(29)&q(30)&q(47)&q(62)&q(61)&q(54)&q(55)&q(28)&q(37)&q(14)&q(35)&q(25)&q(18)&q(3)&q(52)&q(49)&q(10)&q(27)&q(17)&q(36)&q(34)&q(60)&q(59)&q(1)&q(19)&q(57)&q(42)&q(33)&q(44)&q(43)&q(9)&q(58)&q(2)&q(26);
        kkey_6<=q(61)&q(20)&q(37)&q(47)&q(22)&q(54)&q(38)&q(14)&q(4)&q(62)&q(23)&q(29)&q(39)&q(7)&q(45)&q(46)&q(63)&q(13)&q(12)&q(5)&q(6)&q(15)&q(53)&q(30)&q(51)&q(41)&q(34)&q(19)&q(1)&q(2)&q(26)&q(43)&q(33)&q(52)&q(50)&q(9)&q(44)&q(17)&q(35)&q(10)&q(58)&q(49)&q(60)&q(59)&q(25)&q(11)&q(18)&q(42);
        kkey_7<=q(12)&q(7)&q(53)&q(63)&q(38)&q(5)&q(54)&q(30)&q(20)&q(13)&q(39)&q(45)&q(55)&q(23)&q(61)&q(62)&q(14)&q(29)&q(28)&q(21)&q(22)&q(31)&q(4)&q(46)&q(36)&q(57)&q(50)&q(35)&q(17)&q(18)&q(42)&q(59)&q(49)&q(1)&q(3)&q(25)&q(60)&q(33)&q(51)&q(26)&q(11)&q(2)&q(9)&q(44)&q(41)&q(27)&q(34)&q(58);
        kkey_8<=q(28)&q(23)&q(4)&q(14)&q(54)&q(21)&q(5)&q(46)&q(7)&q(29)&q(55)&q(61)&q(6)&q(39)&q(12)&q(13)&q(30)&q(45)&q(15)&q(37)&q(38)&q(47)&q(20)&q(62)&q(52)&q(10)&q(3)&q(51)&q(33)&q(34)&q(58)&q(44)&q(2)&q(17)&q(19)&q(41)&q(9)&q(49)&q(36)&q(42)&q(27)&q(18)&q(25)&q(60)&q(57)&q(43)&q(50)&q(11);
        kkey_9<=q(7)&q(31)&q(12)&q(22)&q(62)&q(29)&q(13)&q(54)&q(15)&q(37)&q(63)&q(4)&q(14)&q(47)&q(20)&q(21)&q(38)&q(53)&q(23)&q(45)&q(46)&q(55)&q(28)&q(5)&q(60)&q(18)&q(11)&q(59)&q(41)&q(42)&q(3)&q(52)&q(10)&q(25)&q(27)&q(49)&q(17)&q(57)&q(44)&q(50)&q(35)&q(26)&q(33)&q(1)&q(2)&q(51)&q(58)&q(19);
        kkey_10<=q(23)&q(47)&q(28)&q(38)&q(13)&q(45)&q(29)&q(5)&q(31)&q(53)&q(14)&q(20)&q(30)&q(63)&q(7)&q(37)&q(54)&q(4)&q(39)&q(61)&q(62)&q(6)&q(15)&q(21)&q(9)&q(34)&q(27)&q(44)&q(57)&q(58)&q(19)&q(1)&q(26)&q(41)&q(43)&q(2)&q(33)&q(10)&q(60)&q(3)&q(51)&q(42)&q(49)&q(17)&q(18)&q(36)&q(11)&q(35);
        kkey_11<=q(39)&q(63)&q(15)&q(54)&q(29)&q(61)&q(45)&q(21)&q(47)&q(4)&q(30)&q(7)&q(46)&q(14)&q(23)&q(53)&q(5)&q(20)&q(55)&q(12)&q(13)&q(22)&q(31)&q(37)&q(25)&q(50)&q(43)&q(60)&q(10)&q(11)&q(35)&q(17)&q(42)&q(57)&q(59)&q(18)&q(49)&q(26)&q(9)&q(19)&q(36)&q(58)&q(2)&q(33)&q(34)&q(52)&q(27)&q(51);
        kkey_12<=q(55)&q(14)&q(31)&q(5)&q(45)&q(12)&q(61)&q(37)&q(63)&q(20)&q(46)&q(23)&q(62)&q(30)&q(39)&q(4)&q(21)&q(7)&q(6)&q(28)&q(29)&q(38)&q(47)&q(53)&q(41)&q(3)&q(59)&q(9)&q(26)&q(27)&q(51)&q(33)&q(58)&q(10)&q(44)&q(34)&q(2)&q(42)&q(25)&q(35)&q(52)&q(11)&q(18)&q(49)&q(50)&q(1)&q(43)&q(36);
        kkey_13<=q(6)&q(30)&q(47)&q(21)&q(61)&q(28)&q(12)&q(53)&q(14)&q(7)&q(62)&q(39)&q(13)&q(46)&q(55)&q(20)&q(37)&q(23)&q(22)&q(15)&q(45)&q(54)&q(63)&q(4)&q(57)&q(19)&q(44)&q(25)&q(42)&q(43)&q(36)&q(49)&q(11)&q(26)&q(60)&q(50)&q(18)&q(58)&q(41)&q(51)&q(1)&q(27)&q(34)&q(2)&q(3)&q(17)&q(59)&q(52);
        kkey_14<=q(22)&q(46)&q(63)&q(37)&q(12)&q(15)&q(28)&q(4)&q(30)&q(23)&q(13)&q(55)&q(29)&q(62)&q(6)&q(7)&q(53)&q(39)&q(38)&q(31)&q(61)&q(5)&q(14)&q(20)&q(10)&q(35)&q(60)&q(41)&q(58)&q(59)&q(52)&q(2)&q(27)&q(42)&q(9)&q(3)&q(34)&q(11)&q(57)&q(36)&q(17)&q(43)&q(50)&q(18)&q(19)&q(33)&q(44)&q(1);
        kkey_15<=q(38)&q(62)&q(14)&q(53)&q(28)&q(31)&q(15)&q(20)&q(46)&q(39)&q(29)&q(6)&q(45)&q(13)&q(22)&q(23)&q(4)&q(55)&q(54)&q(47)&q(12)&q(21)&q(30)&q(7)&q(26)&q(51)&q(9)&q(57)&q(11)&q(44)&q(1)&q(18)&q(43)&q(58)&q(25)&q(19)&q(50)&q(27)&q(10)&q(52)&q(33)&q(59)&q(3)&q(34)&q(35)&q(49)&q(60)&q(17);
        kkey_16<=q(46)&q(5)&q(22)&q(61)&q(7)&q(39)&q(23)&q(28)&q(54)&q(47)&q(37)&q(14)&q(53)&q(21)&q(30)&q(31)&q(12)&q(63)&q(62)&q(55)&q(20)&q(29)&q(38)&q(15)&q(34)&q(59)&q(17)&q(2)&q(19)&q(52)&q(9)&q(26)&q(51)&q(3)&q(33)&q(27)&q(58)&q(35)&q(18)&q(60)&q(41)&q(36)&q(11)&q(42)&q(43)&q(57)&q(1)&q(25);
    end process;


    P2 : process(sel,kkey_1,kkey_2,kkey_3,kkey_4,kkey_5,kkey_6,kkey_7,kkey_8,kkey_9,kkey_10,kkey_11,kkey_12,kkey_13,kkey_14,kkey_15,kkey_16)
    begin
        if (sel(0)='0') then
            s0_0 <= kkey_1;
            s0_1 <= kkey_3;
            s0_2 <= kkey_5;
            s0_3 <= kkey_7;
            s0_4 <= kkey_9;
            s0_5 <= kkey_11;
            s0_6 <= kkey_13;
            s0_7 <= kkey_15;
        else
            s0_0 <= kkey_2;
            s0_1 <= kkey_4;
            s0_2 <= kkey_6;
            s0_3 <= kkey_8;
            s0_4 <= kkey_10;
            s0_5 <= kkey_12;
            s0_6 <= kkey_14;
            s0_7 <= kkey_16;
        end if;
    end process;


    P3 : process(sel,s0_0,s0_1,s0_2,s0_3,s0_4,s0_5,s0_6,s0_7)
    begin
        if (sel(1)='0') then
            s1_0 <= s0_0;
            s1_1 <= s0_2;
            s1_2 <= s0_4;
            s1_3 <= s0_6;
        else
            s1_0 <= s0_1;
            s1_1 <= s0_3;
            s1_2 <= s0_5;
            s1_3 <= s0_7;
        end if;
    end process;


    P4 : process(sel,s1_0,s1_1,s1_2,s1_3)
    begin
        if (sel(2)='0') then
            s2_0 <= s1_0;
            s2_1 <= s1_2;
        else
            s2_0 <= s1_1;
            s2_1 <= s1_3;
        end if;
    end process;


    P5 : process(sel,s2_0,s2_1)
    begin
        if (sel(3)='0') then
            subkey <= s2_0;
        else
            subkey <= s2_1;
        end if;
    end process;


end simple;


--------------------------------------------------------------------------
------------------------------------------------------ SUBS_1 ------------
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity subs_1 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_1 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_1 is
begin
    P6 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1110";
            when "000001" => sortie<="0000";
            when "000010" => sortie<="0100";
            when "000011" => sortie<="1111";
            when "000100" => sortie<="1101";
            when "000101" => sortie<="0111";
            when "000110" => sortie<="0001";
            when "000111" => sortie<="0100";
            when "001000" => sortie<="0010";
            when "001001" => sortie<="1110";
            when "001010" => sortie<="1111";
            when "001011" => sortie<="0010";
            when "001100" => sortie<="1011";
            when "001101" => sortie<="1101";
            when "001110" => sortie<="1000";
            when "001111" => sortie<="0001";
            when "010000" => sortie<="0011";
            when "010001" => sortie<="1010";
            when "010010" => sortie<="1010";
            when "010011" => sortie<="0110";
            when "010100" => sortie<="0110";
            when "010101" => sortie<="1100";
            when "010110" => sortie<="1100";
            when "010111" => sortie<="1011";
            when "011000" => sortie<="0101";
            when "011001" => sortie<="1001";
            when "011010" => sortie<="1001";
            when "011011" => sortie<="0101";
            when "011100" => sortie<="0000";
            when "011101" => sortie<="0011";
            when "011110" => sortie<="0111";
            when "011111" => sortie<="1000";
            when "100000" => sortie<="0100";
            when "100001" => sortie<="1111";
            when "100010" => sortie<="0001";
            when "100011" => sortie<="1100";
            when "100100" => sortie<="1110";
            when "100101" => sortie<="1000";
            when "100110" => sortie<="1000";
            when "100111" => sortie<="0010";
            when "101000" => sortie<="1101";
            when "101001" => sortie<="0100";
            when "101010" => sortie<="0110";
            when "101011" => sortie<="1001";
            when "101100" => sortie<="0010";
            when "101101" => sortie<="0001";
            when "101110" => sortie<="1011";
            when "101111" => sortie<="0111";
            when "110000" => sortie<="1111";
            when "110001" => sortie<="0101";
            when "110010" => sortie<="1100";
            when "110011" => sortie<="1011";
            when "110100" => sortie<="1001";
            when "110101" => sortie<="0011";
            when "110110" => sortie<="0111";
            when "110111" => sortie<="1110";
            when "111000" => sortie<="0011";
            when "111001" => sortie<="1010";
            when "111010" => sortie<="1010";
            when "111011" => sortie<="0000";
            when "111100" => sortie<="0101";
            when "111101" => sortie<="0110";
            when "111110" => sortie<="0000";
            when others   => sortie<="1101";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_2 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_2 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_2 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_2 is
begin
    P7 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1111";
            when "000001" => sortie<="0011";
            when "000010" => sortie<="0001";
            when "000011" => sortie<="1101";
            when "000100" => sortie<="1000";
            when "000101" => sortie<="0100";
            when "000110" => sortie<="1110";
            when "000111" => sortie<="0111";
            when "001000" => sortie<="0110";
            when "001001" => sortie<="1111";
            when "001010" => sortie<="1011";
            when "001011" => sortie<="0010";
            when "001100" => sortie<="0011";
            when "001101" => sortie<="1000";
            when "001110" => sortie<="0100";
            when "001111" => sortie<="1110";
            when "010000" => sortie<="1001";
            when "010001" => sortie<="1100";
            when "010010" => sortie<="0111";
            when "010011" => sortie<="0000";
            when "010100" => sortie<="0010";
            when "010101" => sortie<="0001";
            when "010110" => sortie<="1101";
            when "010111" => sortie<="1010";
            when "011000" => sortie<="1100";
            when "011001" => sortie<="0110";
            when "011010" => sortie<="0000";
            when "011011" => sortie<="1001";
            when "011100" => sortie<="0101";
            when "011101" => sortie<="1011";
            when "011110" => sortie<="1010";
            when "011111" => sortie<="0101";
            when "100000" => sortie<="0000";
            when "100001" => sortie<="1101";
            when "100010" => sortie<="1110";
            when "100011" => sortie<="1000";
            when "100100" => sortie<="0111";
            when "100101" => sortie<="1010";
            when "100110" => sortie<="1011";
            when "100111" => sortie<="0001";
            when "101000" => sortie<="1010";
            when "101001" => sortie<="0011";
            when "101010" => sortie<="0100";
            when "101011" => sortie<="1111";
            when "101100" => sortie<="1101";
            when "101101" => sortie<="0100";
            when "101110" => sortie<="0001";
            when "101111" => sortie<="0010";
            when "110000" => sortie<="0101";
            when "110001" => sortie<="1011";
            when "110010" => sortie<="1000";
            when "110011" => sortie<="0110";
            when "110100" => sortie<="1100";
            when "110101" => sortie<="0111";
            when "110110" => sortie<="0110";
            when "110111" => sortie<="1100";
            when "111000" => sortie<="1001";
            when "111001" => sortie<="0000";
            when "111010" => sortie<="0011";
            when "111011" => sortie<="0101";
            when "111100" => sortie<="0010";
            when "111101" => sortie<="1110";
            when "111110" => sortie<="1111";
            when others   => sortie<="1001";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_3 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_3 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_3 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_3 is
begin
    P8 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1010";
            when "000001" => sortie<="1101";
            when "000010" => sortie<="0000";
            when "000011" => sortie<="0111";
            when "000100" => sortie<="1001";
            when "000101" => sortie<="0000";
            when "000110" => sortie<="1110";
            when "000111" => sortie<="1001";
            when "001000" => sortie<="0110";
            when "001001" => sortie<="0011";
            when "001010" => sortie<="0011";
            when "001011" => sortie<="0100";
            when "001100" => sortie<="1111";
            when "001101" => sortie<="0110";
            when "001110" => sortie<="0101";
            when "001111" => sortie<="1010";
            when "010000" => sortie<="0001";
            when "010001" => sortie<="0010";
            when "010010" => sortie<="1101";
            when "010011" => sortie<="1000";
            when "010100" => sortie<="1100";
            when "010101" => sortie<="0101";
            when "010110" => sortie<="0111";
            when "010111" => sortie<="1110";
            when "011000" => sortie<="1011";
            when "011001" => sortie<="1100";
            when "011010" => sortie<="0100";
            when "011011" => sortie<="1011";
            when "011100" => sortie<="0010";
            when "011101" => sortie<="1111";
            when "011110" => sortie<="1000";
            when "011111" => sortie<="0001";
            when "100000" => sortie<="1101";
            when "100001" => sortie<="0001";
            when "100010" => sortie<="0110";
            when "100011" => sortie<="1010";
            when "100100" => sortie<="0100";
            when "100101" => sortie<="1101";
            when "100110" => sortie<="1001";
            when "100111" => sortie<="0000";
            when "101000" => sortie<="1000";
            when "101001" => sortie<="0110";
            when "101010" => sortie<="1111";
            when "101011" => sortie<="1001";
            when "101100" => sortie<="0011";
            when "101101" => sortie<="1000";
            when "101110" => sortie<="0000";
            when "101111" => sortie<="0111";
            when "110000" => sortie<="1011";
            when "110001" => sortie<="0100";
            when "110010" => sortie<="0001";
            when "110011" => sortie<="1111";
            when "110100" => sortie<="0010";
            when "110101" => sortie<="1110";
            when "110110" => sortie<="1100";
            when "110111" => sortie<="0011";
            when "111000" => sortie<="0101";
            when "111001" => sortie<="1011";
            when "111010" => sortie<="1010";
            when "111011" => sortie<="0101";
            when "111100" => sortie<="1110";
            when "111101" => sortie<="0010";
            when "111110" => sortie<="0111";
            when others   => sortie<="1100";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_4 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_4 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_4 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_4 is
begin
    P9 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="0111";
            when "000001" => sortie<="1101";
            when "000010" => sortie<="1101";
            when "000011" => sortie<="1000";
            when "000100" => sortie<="1110";
            when "000101" => sortie<="1011";
            when "000110" => sortie<="0011";
            when "000111" => sortie<="0101";
            when "001000" => sortie<="0000";
            when "001001" => sortie<="0110";
            when "001010" => sortie<="0110";
            when "001011" => sortie<="1111";
            when "001100" => sortie<="1001";
            when "001101" => sortie<="0000";
            when "001110" => sortie<="1010";
            when "001111" => sortie<="0011";
            when "010000" => sortie<="0001";
            when "010001" => sortie<="0100";
            when "010010" => sortie<="0010";
            when "010011" => sortie<="0111";
            when "010100" => sortie<="1000";
            when "010101" => sortie<="0010";
            when "010110" => sortie<="0101";
            when "010111" => sortie<="1100";
            when "011000" => sortie<="1011";
            when "011001" => sortie<="0001";
            when "011010" => sortie<="1100";
            when "011011" => sortie<="1010";
            when "011100" => sortie<="0100";
            when "011101" => sortie<="1110";
            when "011110" => sortie<="1111";
            when "011111" => sortie<="1001";
            when "100000" => sortie<="1010";
            when "100001" => sortie<="0011";
            when "100010" => sortie<="0110";
            when "100011" => sortie<="1111";
            when "100100" => sortie<="1001";
            when "100101" => sortie<="0000";
            when "100110" => sortie<="0000";
            when "100111" => sortie<="0110";
            when "101000" => sortie<="1100";
            when "101001" => sortie<="1010";
            when "101010" => sortie<="1011";
            when "101011" => sortie<="0001";
            when "101100" => sortie<="0111";
            when "101101" => sortie<="1101";
            when "101110" => sortie<="1101";
            when "101111" => sortie<="1000";
            when "110000" => sortie<="1111";
            when "110001" => sortie<="1001";
            when "110010" => sortie<="0001";
            when "110011" => sortie<="0100";
            when "110100" => sortie<="0011";
            when "110101" => sortie<="0101";
            when "110110" => sortie<="1110";
            when "110111" => sortie<="1011";
            when "111000" => sortie<="0101";
            when "111001" => sortie<="1100";
            when "111010" => sortie<="0010";
            when "111011" => sortie<="0111";
            when "111100" => sortie<="1000";
            when "111101" => sortie<="0010";
            when "111110" => sortie<="0100";
            when others   => sortie<="1110";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_5 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_5 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_5 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_5 is
begin
    P10 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="0010";
            when "000001" => sortie<="1110";
            when "000010" => sortie<="1100";
            when "000011" => sortie<="1011";
            when "000100" => sortie<="0100";
            when "000101" => sortie<="0010";
            when "000110" => sortie<="0001";
            when "000111" => sortie<="1100";
            when "001000" => sortie<="0111";
            when "001001" => sortie<="0100";
            when "001010" => sortie<="1010";
            when "001011" => sortie<="0111";
            when "001100" => sortie<="1011";
            when "001101" => sortie<="1101";
            when "001110" => sortie<="0110";
            when "001111" => sortie<="0001";
            when "010000" => sortie<="1000";
            when "010001" => sortie<="0101";
            when "010010" => sortie<="0101";
            when "010011" => sortie<="0000";
            when "010100" => sortie<="0011";
            when "010101" => sortie<="1111";
            when "010110" => sortie<="1111";
            when "010111" => sortie<="1010";
            when "011000" => sortie<="1101";
            when "011001" => sortie<="0011";
            when "011010" => sortie<="0000";
            when "011011" => sortie<="1001";
            when "011100" => sortie<="1110";
            when "011101" => sortie<="1000";
            when "011110" => sortie<="1001";
            when "011111" => sortie<="0110";
            when "100000" => sortie<="0100";
            when "100001" => sortie<="1011";
            when "100010" => sortie<="0010";
            when "100011" => sortie<="1000";
            when "100100" => sortie<="0001";
            when "100101" => sortie<="1100";
            when "100110" => sortie<="1011";
            when "100111" => sortie<="0111";
            when "101000" => sortie<="1010";
            when "101001" => sortie<="0001";
            when "101010" => sortie<="1101";
            when "101011" => sortie<="1110";
            when "101100" => sortie<="0111";
            when "101101" => sortie<="0010";
            when "101110" => sortie<="1000";
            when "101111" => sortie<="1101";
            when "110000" => sortie<="1111";
            when "110001" => sortie<="0110";
            when "110010" => sortie<="1001";
            when "110011" => sortie<="1111";
            when "110100" => sortie<="1100";
            when "110101" => sortie<="0000";
            when "110110" => sortie<="0101";
            when "110111" => sortie<="1001";
            when "111000" => sortie<="0110";
            when "111001" => sortie<="1010";
            when "111010" => sortie<="0011";
            when "111011" => sortie<="0100";
            when "111100" => sortie<="0000";
            when "111101" => sortie<="0101";
            when "111110" => sortie<="1110";
            when others   => sortie<="0011";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_6 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_6 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_6 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_6 is
begin
    P11 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1100";
            when "000001" => sortie<="1010";
            when "000010" => sortie<="0001";
            when "000011" => sortie<="1111";
            when "000100" => sortie<="1010";
            when "000101" => sortie<="0100";
            when "000110" => sortie<="1111";
            when "000111" => sortie<="0010";
            when "001000" => sortie<="1001";
            when "001001" => sortie<="0111";
            when "001010" => sortie<="0010";
            when "001011" => sortie<="1100";
            when "001100" => sortie<="0110";
            when "001101" => sortie<="1001";
            when "001110" => sortie<="1000";
            when "001111" => sortie<="0101";
            when "010000" => sortie<="0000";
            when "010001" => sortie<="0110";
            when "010010" => sortie<="1101";
            when "010011" => sortie<="0001";
            when "010100" => sortie<="0011";
            when "010101" => sortie<="1101";
            when "010110" => sortie<="0100";
            when "010111" => sortie<="1110";
            when "011000" => sortie<="1110";
            when "011001" => sortie<="0000";
            when "011010" => sortie<="0111";
            when "011011" => sortie<="1011";
            when "011100" => sortie<="0101";
            when "011101" => sortie<="0011";
            when "011110" => sortie<="1011";
            when "011111" => sortie<="1000";
            when "100000" => sortie<="1001";
            when "100001" => sortie<="0100";
            when "100010" => sortie<="1110";
            when "100011" => sortie<="0011";
            when "100100" => sortie<="1111";
            when "100101" => sortie<="0010";
            when "100110" => sortie<="0101";
            when "100111" => sortie<="1100";
            when "101000" => sortie<="0010";
            when "101001" => sortie<="1001";
            when "101010" => sortie<="1000";
            when "101011" => sortie<="0101";
            when "101100" => sortie<="1100";
            when "101101" => sortie<="1111";
            when "101110" => sortie<="0011";
            when "101111" => sortie<="1010";
            when "110000" => sortie<="0111";
            when "110001" => sortie<="1011";
            when "110010" => sortie<="0000";
            when "110011" => sortie<="1110";
            when "110100" => sortie<="0100";
            when "110101" => sortie<="0001";
            when "110110" => sortie<="1010";
            when "110111" => sortie<="0111";
            when "111000" => sortie<="0001";
            when "111001" => sortie<="0110";
            when "111010" => sortie<="1101";
            when "111011" => sortie<="0000";
            when "111100" => sortie<="1011";
            when "111101" => sortie<="1000";
            when "111110" => sortie<="0110";
            when others   => sortie<="1101";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_7 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_7 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_7 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_7 is
begin
    P12 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="0100";
            when "000001" => sortie<="1101";
            when "000010" => sortie<="1011";
            when "000011" => sortie<="0000";
            when "000100" => sortie<="0010";
            when "000101" => sortie<="1011";
            when "000110" => sortie<="1110";
            when "000111" => sortie<="0111";
            when "001000" => sortie<="1111";
            when "001001" => sortie<="0100";
            when "001010" => sortie<="0000";
            when "001011" => sortie<="1001";
            when "001100" => sortie<="1000";
            when "001101" => sortie<="0001";
            when "001110" => sortie<="1101";
            when "001111" => sortie<="1010";
            when "010000" => sortie<="0011";
            when "010001" => sortie<="1110";
            when "010010" => sortie<="1100";
            when "010011" => sortie<="0011";
            when "010100" => sortie<="1001";
            when "010101" => sortie<="0101";
            when "010110" => sortie<="0111";
            when "010111" => sortie<="1100";
            when "011000" => sortie<="0101";
            when "011001" => sortie<="0010";
            when "011010" => sortie<="1010";
            when "011011" => sortie<="1111";
            when "011100" => sortie<="0110";
            when "011101" => sortie<="1000";
            when "011110" => sortie<="0001";
            when "011111" => sortie<="0110";
            when "100000" => sortie<="0001";
            when "100001" => sortie<="0110";
            when "100010" => sortie<="0100";
            when "100011" => sortie<="1011";
            when "100100" => sortie<="1011";
            when "100101" => sortie<="1101";
            when "100110" => sortie<="1101";
            when "100111" => sortie<="1000";
            when "101000" => sortie<="1100";
            when "101001" => sortie<="0001";
            when "101010" => sortie<="0011";
            when "101011" => sortie<="0100";
            when "101100" => sortie<="0111";
            when "101101" => sortie<="1010";
            when "101110" => sortie<="1110";
            when "101111" => sortie<="0111";
            when "110000" => sortie<="1010";
            when "110001" => sortie<="1001";
            when "110010" => sortie<="1111";
            when "110011" => sortie<="0101";
            when "110100" => sortie<="0110";
            when "110101" => sortie<="0000";
            when "110110" => sortie<="1000";
            when "110111" => sortie<="1111";
            when "111000" => sortie<="0000";
            when "111001" => sortie<="1110";
            when "111010" => sortie<="0101";
            when "111011" => sortie<="0010";
            when "111100" => sortie<="1001";
            when "111101" => sortie<="0011";
            when "111110" => sortie<="0010";
            when others   => sortie<="1100";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_8 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_8 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_8 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_8 is
begin
    P13 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1101";
            when "000001" => sortie<="0001";
            when "000010" => sortie<="0010";
            when "000011" => sortie<="1111";
            when "000100" => sortie<="1000";
            when "000101" => sortie<="1101";
            when "000110" => sortie<="0100";
            when "000111" => sortie<="1000";
            when "001000" => sortie<="0110";
            when "001001" => sortie<="1010";
            when "001010" => sortie<="1111";
            when "001011" => sortie<="0011";
            when "001100" => sortie<="1011";
            when "001101" => sortie<="0111";
            when "001110" => sortie<="0001";
            when "001111" => sortie<="0100";
            when "010000" => sortie<="1010";
            when "010001" => sortie<="1100";
            when "010010" => sortie<="1001";
            when "010011" => sortie<="0101";
            when "010100" => sortie<="0011";
            when "010101" => sortie<="0110";
            when "010110" => sortie<="1110";
            when "010111" => sortie<="1011";
            when "011000" => sortie<="0101";
            when "011001" => sortie<="0000";
            when "011010" => sortie<="0000";
            when "011011" => sortie<="1110";
            when "011100" => sortie<="1100";
            when "011101" => sortie<="1001";
            when "011110" => sortie<="0111";
            when "011111" => sortie<="0010";
            when "100000" => sortie<="0111";
            when "100001" => sortie<="0010";
            when "100010" => sortie<="1011";
            when "100011" => sortie<="0001";
            when "100100" => sortie<="0100";
            when "100101" => sortie<="1110";
            when "100110" => sortie<="0001";
            when "100111" => sortie<="0111";
            when "101000" => sortie<="1001";
            when "101001" => sortie<="0100";
            when "101010" => sortie<="1100";
            when "101011" => sortie<="1010";
            when "101100" => sortie<="1110";
            when "101101" => sortie<="1000";
            when "101110" => sortie<="0010";
            when "101111" => sortie<="1101";
            when "110000" => sortie<="0000";
            when "110001" => sortie<="1111";
            when "110010" => sortie<="0110";
            when "110011" => sortie<="1100";
            when "110100" => sortie<="1010";
            when "110101" => sortie<="1001";
            when "110110" => sortie<="1101";
            when "110111" => sortie<="0000";
            when "111000" => sortie<="1111";
            when "111001" => sortie<="0011";
            when "111010" => sortie<="0011";
            when "111011" => sortie<="0101";
            when "111100" => sortie<="0101";
            when "111101" => sortie<="0110";
            when "111110" => sortie<="1000";
            when others   => sortie<="1011";
        end case;
    end process;


end simple;






--------------------------------------------------------------------------
---------------------------------------------------- TCDG   --------------
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity tcdg is
    port (
        key   : in  std_logic_vector(63 downto 0);
        d     : in  std_logic_vector(63 downto 0);
        start : in  std_logic;
        crypt : in  std_logic;
        clk   : in  std_logic;
        nreset: in  std_logic;
        q     : out std_logic_vector(63 downto 0);
        done  : out std_logic
    );
end;


-------------------- Architecture tcdg --------------------------------

library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of TCDG is

    component subkey 
    port (
         key    : in  std_logic_vector(63 downto 0);
         sel    : in  std_logic_vector(3 downto 0);
         subkey : out std_logic_vector(47 downto 0)
    );
    end component;



    component subs_1 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_1 : std_logic_vector(3 downto 0);
    signal s_in_1  : std_logic_vector(5 downto 0);

    component subs_2 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_2 : std_logic_vector(3 downto 0);
    signal s_in_2  : std_logic_vector(5 downto 0);

    component subs_3 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_3 : std_logic_vector(3 downto 0);
    signal s_in_3  : std_logic_vector(5 downto 0);

    component subs_4 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_4 : std_logic_vector(3 downto 0);
    signal s_in_4  : std_logic_vector(5 downto 0);

    component subs_5 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_5 : std_logic_vector(3 downto 0);
    signal s_in_5  : std_logic_vector(5 downto 0);

    component subs_6 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_6 : std_logic_vector(3 downto 0);
    signal s_in_6  : std_logic_vector(5 downto 0);

    component subs_7 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_7 : std_logic_vector(3 downto 0);
    signal s_in_7  : std_logic_vector(5 downto 0);

    component subs_8 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_8      : std_logic_vector(3 downto 0);
    signal s_in_8       : std_logic_vector(5 downto 0);


    signal xorkey       : std_logic_vector(47 downto 0);
    signal w            : std_logic_vector(31 downto 0);
    signal t            : std_logic_vector(31 downto 0);
    signal kkey         : std_logic_vector(47 downto 0);
    signal erkey        : std_logic_vector(47 downto 0);
    signal rkey         : std_logic_vector(31 downto 0);
    signal lkey         : std_logic_vector(31 downto 0);
    signal r0           : std_logic_vector(31 downto 0);
    signal l0           : std_logic_vector(31 downto 0);
    signal state        : std_logic_vector( 3 downto 0);
    signal next_state   : std_logic_vector( 3 downto 0);
    signal rkeyreg      : std_logic_vector(31 downto 0);
    signal next_rkeyreg : std_logic_vector(31 downto 0);
    signal pnewbkey     : std_logic_vector(31 downto 0);
    signal rkey_in      : std_logic_vector(31 downto 0);
    signal lkeyreg      : std_logic_vector(31 downto 0);
    signal next_lkeyreg : std_logic_vector(31 downto 0);
    signal k            : std_logic_vector(63 downto 0);
    signal datainreg    : std_logic_vector(63 downto 0);
    signal id           : std_logic_vector(63 downto 0);
    signal keysel       : std_logic_vector(3 downto 0);
    signal start_prev   : std_logic;
    signal ff_crypt     : std_logic;
    signal next_ff_crypt: std_logic;

begin


    P14 : process(state,ff_crypt)
    begin
            if (ff_crypt='1') then 
            keysel <= state;
        else
            keysel <= not state;
        end if;
    end process;


    i_subkey : subkey
    port map (key => key, sel => keysel,subkey => kkey );


    id <= datainreg;


    l0<=id(6)&id(14)&id(22)&id(30)&id(38)&id(46)&id(54)&id(62)&id(4)&id(12)&id(20)&id(28)&id(36)&id(44)&id(52)&id(60)&id(2)&id(10)&id(18)&id(26)&id(34)&id(42)&id(50)&id(58)&id(0)&id(8)&id(16)&id(24)&id(32)&id(40)&id(48)&id(56);
    r0<=id(7)&id(15)&id(23)&id(31)&id(39)&id(47)&id(55)&id(63)&id(5)&id(13)&id(21)&id(29)&id(37)&id(45)&id(53)&id(61)&id(3)&id(11)&id(19)&id(27)&id(35)&id(43)&id(51)&id(59)&id(1)&id(9)&id(17)&id(25)&id(33)&id(41)&id(49)&id(57);


    P17 : process(state,r0,rkeyreg,l0,lkeyreg)
    begin
        if (state="0000") then 
            rkey_in <= r0;
            lkey    <= l0;
        else
            rkey_in <= rkeyreg;
            lkey    <= lkeyreg;
        end if;
    end process;


    t <= rkey_in;


    erkey<=t(0)&t(31 downto 27)&t(28 downto 23)&t(24 downto 19)&t(20 downto 15)&t(16 downto 11)&t(12 downto 7)&t(8 downto 3)&t(4 downto 0)&t(31);

    xorkey <= erkey xor kkey;
    s_in_1 <= xorkey(47 downto 42);
    s_in_2 <= xorkey(41 downto 36);
    s_in_3 <= xorkey(35 downto 30);
    s_in_4 <= xorkey(29 downto 24);
    s_in_5 <= xorkey(23 downto 18);
    s_in_6 <= xorkey(17 downto 12);
    s_in_7 <= xorkey(11 downto  6);
    s_in_8 <= xorkey( 5 downto  0);
    
    i_subs_1 : subs_1
    port map (entree => s_in_1,sortie => s_out_1);

    i_subs_2 : subs_2
    port map (entree => s_in_2,sortie => s_out_2);

    i_subs_3 : subs_3
    port map (entree => s_in_3,sortie => s_out_3);

    i_subs_4 : subs_4
    port map (entree => s_in_4,sortie => s_out_4);

    i_subs_5 : subs_5
    port map (entree => s_in_5,sortie => s_out_5);

    i_subs_6 : subs_6
    port map (entree => s_in_6,sortie => s_out_6);

    i_subs_7 : subs_7
    port map (entree => s_in_7,sortie => s_out_7);

    i_subs_8 : subs_8
    port map (entree => s_in_8,sortie => s_out_8);


    w<=s_out_1&s_out_2&s_out_3&s_out_4&s_out_5&s_out_6&s_out_7&s_out_8;

    pnewbkey<=w(16)&w(25)&w(12)&w(11)&w(3)&w(20)&w(4)&w(15)&w(31)&w(17)&w(9)&w(6)&w(27)&w(14)&w(1)&w(22)&w(30)&w(24)&w(8)&w(18)&w(0)&w(5)&w(29)&w(23)&w(13)&w(19)&w(2)&w(26)&w(10)&w(21)&w(28)&w(7);


    rkey <= pnewbkey xor lkey;
    k    <= rkey & rkeyreg;

    q<=k(24)&k(56)&k(16)&k(48)&k(8)&k(40)&k(0)&k(32)&k(25)&k(57)&k(17)&k(49)&k(9)&k(41)&k(1)&k(33)&k(26)&k(58)&k(18)&k(50)&k(10)&k(42)&k(2)&k(34)&k(27)&k(59)&k(19)&k(51)&k(11)&k(43)&k(3)&k(35)&k(28)&k(60)&k(20)&k(52)&k(12)&k(44)&k(4)&k(36)&k(29)&k(61)&k(21)&k(53)&k(13)&k(45)&k(5)&k(37)&k(30)&k(62)&k(22)&k(54)&k(14)&k(46)&k(6)&k(38)&k(31)&k(63)&k(23)&k(55)&k(15)&k(47)&k(7)&k(39);


    P27 : process(start,start_prev,state)
    begin
        if ((start='1') AND (start_prev='0')) then 
            next_state <= "0000";
        else
            if (state="1111") then 
                next_state <= "1111";
            else
                next_state <= state + "1";
            end if;
        end if;
    end process;


    P27_2 : process(start,crypt,ff_crypt,start_prev)
    begin
        if ((start='1') AND (start_prev='0')) then 
            next_ff_crypt <= crypt;
        else
            next_ff_crypt <= ff_crypt;
        end if;
    end process;


    P28 : process(rkeyreg,lkeyreg,state,rkey,rkey_in)
    begin
        if (state="1111") then 
            next_rkeyreg <= rkeyreg;
            next_lkeyreg <= lkeyreg;
            done <= '1';
        else
            next_rkeyreg <= rkey;
            next_lkeyreg <= rkey_in;
            done <= '0';
        end if;
    end process;

    ------------------------------------------------------------- 
        ---------------------------  MEMORIES  ---------------------- 
        ------------------------------------------------------------- 
    P29 : process(clk, nreset)
    begin
        if (nreset='0') then
            state      <= (others => '0');
            rkeyreg    <= (others => '0');
            lkeyreg    <= (others => '0');
            start_prev <= '0';
            datainreg  <= (others => '0');
            ff_crypt   <= '0';
        else
            if (clk='1' and clk'event) then
                state      <= next_state;
                rkeyreg    <= next_rkeyreg;
                lkeyreg    <= next_lkeyreg;
                start_prev <= start;
                datainreg  <= d;
                ff_crypt   <= next_ff_crypt;
            end if;
        end if;
    end process;


end simple;