-- #################################################################### library ieee; use ieee.std_logic_1164.all; entity div16_bench is end; -- ################################################################## library ieee, work; use ieee.std_logic_1164.all; use std.textio.all; architecture simple of div16_bench is component div16 port ( clk : in std_logic; nreset : in std_logic; num : in std_logic_vector(15 downto 0); den : in std_logic_vector(15 downto 0); start : in std_logic; q : in std_logic_vector(15 downto 0); done : out std_logic ); end component ; signal clk : std_logic; signal nreset : std_logic; signal num : std_logic_vector(15 downto 0); signal den : std_logic_vector(15 downto 0); signal start : std_logic; signal q : std_logic_vector(15 downto 0); signal done : std_logic begin i_div : div16 port map ( clk => clk , nreset => nreset , num => num , den => den , start => start , q => q , done => done ); process begin clk <= '0'; wait for 50 ns; clk <= '1'; wait for 50 ns; end process; process begin nreset <= '0'; wait for 20 ns; nreset <= '1'; wait; end process; process procedure calc (constant param1 : in std_logic_vector(15 downto 0); constant param2 : in std_logic_vector(15 downto 0); constant expect : in std_logic_vector(15 downto 0)) is begin num <= param1; den <= param2; start <= '1'; wait for 100 ns; start <= '0'; wait for 900 ns; assert q=expect report "ERROR: calc() output different of expected value" severity error; end calc; -- ============================================================ begin -- vecteurs de test manuel calc(X"0007",X"0004",X"0001"); -- <==== TEST VECTORS ====<<<<===<<< -- vecteurs de test automatique -- a remplir... calc(X"0005",X"0002",X"0002"); calc(X"0005",X"fffe",X"fffe"); calc(X"fffb",X"fffe",X"0002"); calc(X"fffb",X"0002",X"fffe"); calc(X"0004",X"0002",X"0002"); calc(X"0004",X"fffe",X"fffe"); calc(X"fffc",X"fffe",X"0002"); calc(X"fffc",X"0002",X"fffe"); wait; end process; end simple; -- ###################################################################